In the past, test and debug procedures on digital signal processors was done using a scan control unit that converts parallel information from a test and debug unit into a serial data stream. The data values to be scanned out needed to be loaded each time a scan was executed, unless all of the data values were identical.
In a high performance scan controller, the number of times the test and debug unit must load the registers in the scan control unit can become a limiting factor of the performance of the testing procedure. This problem is compounded by the increasing speed of the test clock, which is the speed at which data is serialized and sent to the target processor.
There are two efficiency factors that govern the performance of a test and debug system. These factors are the inherent efficiency of the target processor itself, and the efficiency of the scan control unit. The efficiency of the target processor relates to how many bits of information and control signals must be sent to the target processing unit to perform an operation such as a single step operation, memory access operation, or register access operation. This factor is ignored by this invention since the digital signal processor efficiency cannot be altered by the scan control unit implementation.
The efficiency of the scan control unit relates to how many bits must be loaded into the scan control unit to cause it to send out the required number of bits for the digital signal processor to perform an operation with no dead time between operations. For certain types of operations, the information to be scanned out consists of a fixed value, possibly an opcode, and a variable value, possibly and address or data value.
If a scan control unit has a 16-bit interface with the test and debug unit, and the test clock rate is 32 MHz, the scan control unit must be provided with a data value every 500 ns in order to run at 100% efficiency. In addition, the test and debug unit must load control information into the scan control unit to control the scans and the target processor JTAG interface, as well as access status from the scan control unit related to the scan operations. If the scan control unit access time and test and debug unit memory access times are on the order of 100 ns, then 40% of the bus bandwidth is consumed just by data transfers to the target signal processor. If the target processor is also returning information, then data transfers will be consuming 80% of the bus bandwidth. If the test and debug unit must access the scan controller to determine if a data value can be loaded or read, the remaining 20% of the bus bandwidth is used up, leaving no time for loading control information into the scan controller, or execution of instructions by the test and debug unit.
These limitations can be addressed in 3 ways, widen the data path between the test and debug unit and the scan control unit and memory, reduce the access time, and reduce the number of times the scan control unit must be accessed. Widening the data path requires additional pins on the scan controller device, the debug unit and the memory, and may not always be possible. Reducing the access time of the scan control unit or memory might be possible, but is limited by the particular implementation of both. Reducing the number of accesses of the scan control unit provides a means of improving the efficiency, which can be applied in conjunction with the other two techniques.
Referring to FIG. 1, a block diagram of a test and debug system capable of advantageously using the present invention is shown. The test and debug system includes a user interface 5, a test and debug unit 10, and a target processor 15. The user interface 5 includes the apparatus that permits a user to interact with, and control the testing of, the target processing unit 15. The user interface 5 can include display apparatus, input apparatus such as a keyboard, etc. for initiating test and debug procedures and for receiving the results of these procedures. The user interface 5 is coupled to the test and debug unit 10 through interface unit 101. The interface unit 101 exchanges signals with the processing unit 102 of the test and debug unit 10. The processing unit 102 applies signals to and receives signals from the scan control unit 103. The scan control unit 103 includes a local processor 1031, and memory unit out 1032 for exchanging signals with the local processor 1031, a memory unit in 1035 for storing signals from the target processing unit 15, a shift register out 1034 and a shift register in 1033, the shift registers 1033 and 1034 transferring data in and out of the test and debug unit 10 under control of the local processor 1031. For purposes of the present invention, the processing unit 102 provides commands to the scan control unit 103 and supplies the contents of the memory unit 1032. The target processing unit 15 includes a test access port 151, a shift register 152, an instruction register 153, a data register 154, a mini-status register 155 and a data register 156. The test access port 151 is a state machine responsive to test mode select (TMS) signals from the processing unit 102 for controlling the JTAG apparatus in the target processing unit 15. The shift register 152 receives signals from the shift register out 1034 and transfers signals to the shift register in 1033. The shift register 152 applies signals to the instruction register 153 and with the data register 154 and receives signals from the mini-status register 155 and the data register 156.
Referring to FIG. 2, a portion of the contents of the memory unit out 1032, according to the prior art, is illustrated. In particular, the memory unit out 1032 includes a command parameter section 1032A. Examples of the parameters included in the command parameter section are parameters defining a JTAG scan length and parameters defining JTAG end states. A command from the processing unit 102 will include reference to these parameters and these parameters will be accessed and appropriate control signals applied to the test access port 151 by the local processor.
Referring to FIG. 3, the execution of a command is illustrated. When command A is issued, the command active signal is activated. The command active signal allows the go to shift state function, the send/receive function, and the go to end state to be executed by the scan control unit 103. When the command active signal is no longer active, then a next command B can be executed. If a command C is issued while the target processor is still executing command A, command C will fail and be must retried.
In the past, configurations employing a JTAG emulation unit to test and debug a digital signal processor have had to issue a transaction, such as a read memory command, and then issue additional commands to retrieve the data or to determine if the original transaction was successful. The delay between the commands was usually sufficient to allow the target system the opportunity to complete the transaction. Transactions are usually initiated when the JTAG state (machine) transitions through “Update IR” to “Idle” or Pause. (The state diagram for the JTAG test and debug procedure is shown in FIG. 4. The four stable, non-shift JTAG states are indicated in this Figure as states 41, 42, 43 and 44.) New transactions are initiated by entering the “Scan” state. When the target system does not respond in a timely manner, the transaction will fail, and the test and debug unit 10 must retry the transaction. The transaction retries impact the performance of the test and debug configuration and, in the situation involving large data transfers with many retries, can result in a significant degradation of the configuration performance.
When dealing with large, variable amounts of data, registers become impractical. RAMs and FIFOs are well suited to handle large amounts of data. Using RAMs for data storage requires logic to generate addresses and keep track of when the RAMs are full, and what RAM locations contain valid data. Using FIFOs addresses these two RAM issues, but presents others. The problem with using a FIFO is the data gets “consumed” when it is read, it can only be read once. And once data is written to a FIFO, it cannot be “unwritten”.
When a test and debug unit is used to test a target processing unit, scan operations can sometimes fail. They can fail for a variety of reasons, such as the target processing unit has inhibited emulator access during critical sections of code execution, the test and debug system can have insufficient priority to access memory, or the memory system may simply be busy. If a scan control unit is using a FIFO unit for data storage, these failures can result in loss of data or invalid data values being returned.
A need has been felt for apparatus and an associated method having the feature of being able to increase the rate of transfer of information from a test and debug unit to a target processing unit. It would be another feature of the apparatus and associated method to provide an improved put buffer unit for transferring data to a target processing unit. It would be yet another feature of the apparatus and associated method to provide retransmit of signal groups to the target processing unit when a transfer fails. It is a more particular object of the present invention to maintain a signal group in the put buffer unit until a successful transfer of the signal group has taken place. It would be still another feature of the apparatus and associated method to provide signals indicative of the unused capacity of the put buffer memory unit. It is yet another feature of the apparatus and associated method to synchronize the transfer of data from the scan control unit to the target processor.